Compression of images using K-SOM is advantageous
[9] due to their features such as inherent parallelism,
regular topology and relatively small number of welldefined
arithmetic operations involved in its learning
algorithm. These features are favourable for hardware
implementation which is the focus of our research. With
respect to the hardware implementation of a K-SOM
quantizer, a mixed analog and digital approach was presented
in [10]. Its drawback was that the analog techniques
tended to increase circuit density and suffered from
a lack of accuracy due to the impact of noise. Another
hardware-oriented implementation of K-SOM was also
proposed by Soudris et al. [11]. It is, in our opinion,
targeted to be implemented on a SoC (System-On-Chip)
hardware platform with software/hardware co-design
methodology. To rectify the weaknesses of the predecessor
hardware-based K-SOMs, Sudha [9] proposed a fully
hardware target relying on a digital design for a 3D
K-SOM. The design was based on a single instruction
multiple data (SIMD) stream architecture. The proposed
technique was implemented in order to evaluate its performance
for different sizes of the network on an ASIC
(Application-Specific Integrated Circuit). The implementation
results indicated that 30 frames per second of
images of size 512 9 512 with 64 colour palette size were
obtainable. In [12], a similar architecture was ported to
synthesize on an FPGA. Unfortunately, it required two
Xilinxs Virtex Family of FPGA chips to synthesize the
system whose colour palette size was limited to only 8!